Arithmetic and logic units (ALUs), which are an integral part of processing units, have traditionally been implemented with adders, registers and combinational logic circuits. Efforts to achieve speed or compactness in these ALUs have brought forth parallel architectures and implementation in dynamic MOS (metal oxide semiconductor) and dynamic CMOS (complementary MOS) techniques.
Nevertheless, the insatiable demand for faster or more compact ALU designs is fueled by more demanding computations and applications. Therefore, a desire has arisen for an ALU design which exploits parallel architectures, compact and rectangular layouts, and more compact MOS technologies.
It is further desirable to arrive at an ALU design that will permit multiple processing units functioning in parallel to be accommodated on one integrated circuit (IC) device along with sufficient memory capacity.
The present invention provides for an ALU directed to achieve one or more of the advantages as set forth above.